Another Hammer Detail
By Nils Dahl
Date: August 1, 2002
I was just snooping around for more details on hammer. At AMD's web site, the x86-64 section has a small window containing links to interesting white papers on x86-64. One of those is the x86-64 programmer's overview (x86-64_overview.pdf). It makes for a very interesting read, even though it is dated January 2001.
Here is a nice quoted paragraph.
"The x86-64 architecture allows legacy-mode software to load up to 52-bit physical addresses into the PDE and PTE, as limited by the maximum physical-address size supported by a specific implementation. Unsupported physical-address bits are reserved and must be cleared to zero. In the first implementation of the Hammer family of processors legacy-mode software can use up to 40 bits of physical address in PDE and PTE entries. Software must clear bits 51:40 to 0."
Now some people might ask (and with justification) just what the crazy old man is doing, bothering with this obscure tidbit.
What this says is that LEGACY 32-bit software can be modified to use a total of 256 X 8 gigabytes of memory - or maybe 2 terabytes? Hey, what comes after gigabyte anyway?
Somewhere inside the hammer architecture is a full 8-bit address extension capability that allows implementation of 256 blocks of memory, each one 8 gigabytes in size. Now the process of turning on and activating 64-bit mode is a bit more than I am up to absorbing right now. The designers at AMD probably get aspirin by the case lot as part of their benefit package.
But just for fun, let me try to speculate in plain English on a few of the neat things promised for hammer - round one.
The 64-bit mode will run legacy 32-bit and 16-bit operating systems and applications in some compatibility mode boxes - or whatever you want to call them. Hammer will run multiple instances of legacy stuff, concurrently. Anyone care to simulate networked 32-bit systems conveniently on their new hammer boxes? It will be slow but it would cost far less than renting IBM VMOS mainframe time to run multiple instances of Linux and maybe serve until IBM and the incredible Linux teams port Suse's 64-bit hammer Linux to IBM VMOS mainframes - if they have not done so already.
The 64-bit mode of hammer will directly support 256 blocks of memory, each one 8 gigabytes in size. This means that my idea of grafting in extra memory controllers, each supporting another 8 gigabyte block of memory, at different tunneling Hypertransport points within the 8 node maximum size hammer configuration is do-able. In theory. More memory is good. Even if I can't afford a new nForce system right now.
Legacy operating systems and applications will be able to make direct use of far more main memory than the current 8 gigabyte limit, thanks to extra addressing features provided in hammer. Now these extra features are ONLY available in 64-bit mode and its companion compatibility mode. In legacy 32-bit mode, hammer works just like an Athlon XP. You do NOT get the new, improved XMM (formerly SSE and SSE2) superset in 32-bit mode.
Consider the implications for very large databases that use lots of tables. I can and will speculate that IBM's DB2, running under Suse Linux x86 in 64-bit mode, is going to be a significant step upward in power and performance over the current 32-bit legacy version of DB2. I wonder what Larry is doing to keep up.
The search goes on for details of just how AMD is implementing the physical memory addressing in x86-64. In my humble opinion, the memory controller logic inside each hammer chip contains an 8-bit register that can be loaded with the contents of some tables set up during building of 64-bit mode support details. The memory controller is connected to the crossbar switch so that it can be accessed by the local processor or by the Hypertransport connection to all other processors, alternately of course. This just seems to me like the logical way to design things. I would love to see AMD reveal the details of this to confirm or correct my speculations. Others would like to know.
So, in conclusion, I'll quote that famous grandfather of Susan Sto Heilit (famous Discworld personality) - "ARE WE HAVING FUN YET?". If you care to learn all about Susan and her gramps, try reading:
Thief of Time
all works of the incredibly fertile mind of Terry Pratchett, world's greatest writer of fantasy and sf. We share the same taste in hats. He writes books. I buy his books and read them to learn things. Works for me.
just an old man - seeking the whole truth
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