Platform Conference Wrap Up
By: Van Smith
Date: February 5, 2002
High-speed interconnects in general and HyperTransport in particular were popular subjects at Platform Conference. Over ten seminars were dedicated to HyperTransport during the two day event, a strong sign that this technology is rapidly taking off to becoming an accepted industry standard.
We have discussed HyperTransport in some detail in previous articles. To recount some of the highlights, HyperTransport greatly boosts interconnect bandwidths while reducing latencies and pin counts. The technology is flexible so that it can be scaled to different link widths according to bandwidth demands and pin count requirements. The chart below shows the pin counts for the various link width options.
HyperTransport pin counts versus link width
Not only are link widths customizable, but the interlink frequency can also be varied. Shown in the chart below, bandwidth can be scaled from 200 MB/s (PCI bandwidth is something less than 133MB/s) to 12.8 GB/s and higher throughput has been obtained in the lab.
HyperTransport bandwidth versus pin count and frequency
Several new topological HyperTransport features were detailed. In addition to "Tunnel devices" where a component resides on the HyperTransport bus and passes the signal onto additional devices down the HT chain, so-called "Caves," "Bridges" and combination devices were outlined.
Caves are dead-end peripherals. Bridges are Cave devices that also containing HyperTransport host controllers. The graph below shows a few ways to chain together these HT-enabled devices.
Intel's new archnemesis, Broadcom, was showing off HyperTransport being used successfully as a box-to-box interconnect, likely foreshadowing future applications for this flexible technology.
Broadcom has linked two of its MIPS-based BCM1250 platforms using HyperTransport
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