Pat.no

 Title

6,301,159

50% EXE tracking circuit

6,300,661

Mutual implant region used for applying power/ground to a source of a transistor and a well of a substrate

6,300,658

Method for reduced gate aspect ration to improve gap-fill after spacer etch

6,300,207

Depleted sidewall-poly LDD transistor

6,300,205

Method of making a semiconductor device with self-aligned active, lightly-doped drain, and halo regions

6,300,203

Electrolytic deposition of dielectric precursor materials for use in in-laid gate MOS transistors

6,300,182

Field effect transistor having dual gates with asymmetrical doping for reduced threshold voltage

6,300,180

Method for forming an integrated circuit having improved polysilicon resistor structures

6,300,148

Semiconductor structure with a backside protective layer and backside probes and a method for constructing the structure

6,300,145

Ion implantation and laser anneal to create n-doped structures in silicon

6,299,688

Developer nozzle clean combs

6,298,438

System and method for conditional moving an operand from a source register to destination register

6,298,424

Computer system including priorities for memory operations and allowing a higher priority memory operation to interrupt a lower priority memory operation

6,298,423

High performance load/store functional unit and data cache

6,298,396

System for loading a current buffer desciptor register with a value different from current value to cause a previously read buffer descriptor to be read again

6,298,367

Floating point addition pipeline including extreme value, comparison and accumulate functions

6,297,993

Acceleration voltage implementation for a high density flash memory device

6,297,988

Mode indicator for multi-level memory

6,297,644

Multipurpose defect test structure with switchable voltage contrast capability and method of use

6,297,535

Transistor having a gate dielectric which is substantially resistant to drain-side hot carrier injection

6,297,167

In-situ etch of multiple layers during formation of local interconnects

6,297,159

Method and apparatus for chemical polishing using field responsive materials

6,297,157

Time ramped method for plating of high aspect ratio semiconductor vias and channels

6,297,148

Method of forming a silicon bottom anti-reflective coating with reduced junction leakage during salicidation

6,297,146

Low resistivity semiconductor barrier layer manufacturing method

6,297,143

Process for forming a bit-line in a MONOS device

6,297,117

Formation of confined halo regions in field effect transistor

6,297,115

Cmos processs with low thermal budget

6,297,111

Self-aligned channel transistor and method for making same

6,297,107

High dielectric constant materials as gate dielectrics

6,297,083

Method of forming four transistor SRAM cell having a resistor

6,297,065

Method to rework device with faulty metal stack layer

6,296,710

Multi-port gas injector for a vertical furnace used in semiconductor processing

6,296,709

Temperature ramp for vertical diffusion furnace

6,295,594

Dynamic memory allocation suitable for stride-based prefetching

6,295,586

Queue based memory controller

6,295,574

Real time interrupt handling for superscalar processors

6,295,573

Point-to-point interrupt messaging within a multiprocessing computer system

6,295,572

Integrated SCSI and ethernet controller on a PCI local bus

6,295,314

Method and apparatus for partitioning a modem between non-real-time and real-time processing environments

6,295,228

System for programming memory cells

6,295,016

Pipeline analog to digital (A/D) converter with relaxed accuracy requirement for sample and hold stage

6,295,011

Method of coding a number for storing in a memory

6,294,923

Method and system for detecting faults utilizing an AC power supply

6,294,829

Multilayer quadruple gate field effect transistor structure for use in integrated circuit devices

6,294,472

Dual slurry particle sizes for reducing microscratching of wafers

6,294,460

Semiconductor manufacturing method using a high extinction coefficient dielectric photomask

6,294,433

Gate re-masking for deeper source/drain co-implantation processes

6,294,430

Nitridization of the pre-ddi screen oxide

6,294,412

Silicon based lateral tunneling memory cell

6,294,397

Drop-in test structure and abbreviated integrated circuit process flow for characterizing production integrated circuit process flow, topography, and equipment

6,294,396

Monitoring barrier metal deposition for metal interconnect

6,294,395

Back side reactive ion etch

6,293,698

Method for precise temperature sensing and control of semiconductor structures

6,292,884

Reorder buffer employing last in line indication

6,292,483

Apparatus and method for generating an index key for a network switch routing table using a programmable hash function

6,292,467

Apparatus and method of determining a link status between network stations connected to a telephone line medium

6,292,425

Power saving on the fly during reading of data from a memory device

6,292,406

Method and low-power circuits used to generate accurate boosted wordline voltage for flash memory core cells in read mode

6,292,399

Method and low-power circuits used to generate accurate drain voltage for flash memory core cells in read mode

6,292,049

Circuit and method for reducing voltage oscillations on a digital integrated circuit

6,291,887

Dual damascene arrangements for metal interconnection with low k dielectric constant materials and nitride middle etch stop layer

6,291,864

Gate structure having polysilicon layer with recessed side portions

6,291,860

Self-aligned contacts to source/drain silicon electrodes utilizing polysilicon and silicides

6,291,832

Resonant tunneling diode latch

6,291,348

Method of forming Cu-Ca-O thin films on Cu surfaces in a chemical solution and semiconductor device thereby formed

6,291,339

Bilayer interlayer dielectric having a substantially uniform composite interlayer dielectric constant over pattern features of varying density and method of making the same

6,291,332

Electroless plated semiconductor vias and channels

6,291,329

Protective oxide buffer layer for ARC removal

6,291,302

Selective laser anneal process using highly reflective aluminum mask

6,291,296

Method for removing anti-reflective coating layer using plasma etch process before contact CMP

6,291,278

Method of forming transistors with self aligned damascene gate contact

6,291,253

Feedback control of deposition thickness based on polish planarization

6,291,252

Automatic method to eliminate first-wafer effect

6,291,137

Sidewall formation for sidewall patterning of sub 100 nm structures

6,291,135

Ionization technique to reduce defects on next generation lithography mask during exposure

6,291,113

Sidelobe suppressing phase shift mask and method

6,291,082

Method of electroless ag layer formation for cu interconnects

6,289,468

Technique for controlling system bus timing with on-chip programmable delay lines

6,289,442

Circuit and method for tagging and invalidating speculatively executed instructions

6,288,951

Method and apparatus for continuously regulating a charge pump output voltage using a capacitor divider

6,288,448

Semiconductor interconnect barrier of boron silicon nitride and manufacturing method therefor

6,288,432

Semiconductor fabrication employing a post-implant anneal within a low temperature, high pressure nitrogen ambient to improve channel and gate oxide reliability

6,288,411

Defect collecting structures for photolithography

6,287,968

Method of defining copper seed layer for selective electroless plating processing

6,287,959

Deep submicron metallization using deep UV photoresist

6,287,953

Minimizing transistor size in integrated circuits

6,287,925

Formation of highly conductive junctions by rapid thermal anneal and laser thermal process

6,287,922

Method for fabricating graded LDD transistor using controlled polysilicon gate profile

6,287,918

Process for fabricating a metal semiconductor device component by lateral oxidization

6,287,917

Process for fabricating an MNOS flash memory device

6,287,904

Two step mask process to eliminate gate end cap shortening

6,287,877

Electrically quantifying transistor spacer width

6,286,081

Mechanism for ensuring data coherency during sequential readings of portions of data that changes with time

6,285,627

Address transition detector architecture for a high density flash memory device

6,285,601

Method and apparatus for multi-level buffer thresholds for higher efficiency data transfers

6,285,599

Decoded source lines to tighten erase Vt distribution

6,285,594

Wordline voltage protection

6,285,588

Erase scheme to tighten the threshold voltage distribution of EEPROM flash memory cells

6,285,583

High speed sensing to detect write protect state in a flash memory device 

6,285,181

Method and system for determining the location of an open circuit in a semiconductor device using power modulation 

6,285,133

Ion implanter with multi-level vacuum 

6,285,054

Trenched gate non-volatile semiconductor device with the source/drain regions spaced from the trench by sidewall dopings 

6,285,052

Integrated capacitor 

6,285,036

Endpoint detection for thinning of silicon of a flip chip bonded integrated circuit 

6,284,672

Method of forming a super-shallow amorphous layer in silicon 

6,284,636

Tungsten gate method and apparatus 

6,284,630

Method for fabrication of abrupt drain and source extensions for a field effect transistor 

6,284,622

Method for filling trenches 

6,284,608

Method for making accumulation mode N-channel SOI 

6,284,602

Process to reduce post cycling program VT dispersion for NAND flash memory devices 

6,284,600

Species implantation for minimizing interface defect density in flash memory devices 

6,284,582

MOS-gate tunneling-injection bipolar transistor 

6,284,553

Location dependent automatic defect classification 

6,283,113

Strip separation tool 

6,282,639

Configurable branch prediction for a processor performing speculative execution 

6,281,666

Efficiency of a multiphase switching power supply during low power mode 

6,281,587

Multi-layered coaxial interconnect structure 

6,281,584

Integrated circuit with improved adhesion between interfaces of conductive and dielectric surfaces 

6,281,559

Gate stack structure for variable threshold voltage 

6,281,555

Integrated circuit having isolation structures 

6,281,132

Device and method for etching nitride spacers formed upon an integrated circuit gate conductor 

6,281,130

Method for developing ultra-thin resist films 

6,281,121

Damascene metal interconnects using highly directional deposition of barrier and/or seed layers including (III) filling metal 

6,281,086

Semiconductor device having a low resistance gate conductor and method of fabrication the same 

6,281,078

Manufacturing process to eliminate ONO fence material in high density NAND-type flash memory devices 

6,281,029

Probe points for heat dissipation during testing of flip chip IC 

6,281,028

LED alignment points for semiconductor die 

6,281,025

Substrate removal as a function of SIMS analysis 

6,279,147

Use of an existing product map as a background for making test masks 

6,279,107

Branch selectors associated with byte ranges within an instruction cache for rapidly identifying branch predictions 

6,279,106

Method for reducing branch target storage by calculating direct branch targets on the fly 

6,279,101

Instruction decoder/dispatch 

6,279,058

Master isochronous clock structure having a clock controller coupling to a CPU and two data buses 

6,279,044

Network interface for changing byte alignment transferring on a host bus according to master and slave mode memory and I/O mapping requests 

6,278,308

Low-power flip-flop circuit employing an asymmetric differential stage 

6,278,181

Stacked multi-chip modules using C4 interconnect technology having improved thermal management 

6,278,166

Use of nitric oxide surface anneal to provide reaction barrier for deposition of tantalum pentoxide 

6,277,744

Two-level silane nucleation for blanket tungsten deposition 

6,277,698

Method of manufacturing semiconductor devices having uniform, fully doped gate electrodes 

6,277,690

Elimination of N+ implant from flash technologies by replacement with standard medium-doped-drain (Mdd) implant 

6,277,661

Method for detecting sloped contact holes using a critical-dimension waveform 

6,277,659

Substrate removal using thermal analysis 

6,277,544

Reverse lithographic process for semiconductor spaces 

6,276,989

Method and apparatus for controlling within-wafer uniformity in chemical mechanical polishing 

6,276,038

Apparatus for gripping a plug of an IC package container during removal of the plug 

6,275,975

Scalable mesh architecture with reconfigurable paths for an on-chip data transfer network incorporating a network configuration manager 

6,275,972

Method for accurate channel-length extraction in MOSFETs 

6,275,927

Compressing variable-length instruction prefix bytes 

6,275,905

Messaging scheme to maintain cache coherency and conserve system memory bandwidth during a memory read operation in a multiprocessing computer system 

6,275,894

Bank selector circuit for a simultaneous operation flash memory device with a flexible bank partition architecture 

6,275,782

Non-intrusive performance monitoring 

6,275,424

Reduction of voltage stress across a gate oxide and across a junction within a high voltage transistor of an erasable memory device 

6,275,421

Chip enable input buffer 

6,275,415

Multiple byte channel hot electron programming using ramped gate and source bias voltage 

6,275,414

Uniform bitline strapping of a non-volatile memory cell 

6,275,412

Common flash interface implementation for a simultaneous operation flash memory device 

6,274,915

Method of improving MOS device performance by controlling degree of depletion in the gate electrode 

6,274,894

Low-bandgap source and drain formation for short-channel MOS transistors 

6,274,511

Method of forming junction-leakage free metal silicide in a semiconductor wafer by amorphization of refractory metal layer 

6,274,504

Minimizing metal corrosion during post metal solvent clean 

6,274,501

Formation of structure to accurately measure source/drain resistance 

6,274,475

Specialized metal profile for via landing areas 

6,274,473

Flip chip packages 

6,274,472

Tungsten interconnect method 

6,274,469

Process using a plug as a mask for a gate 

6,274,443

Simplified graded LDD transistor using controlled polysilicon gate profile 

6,274,442

Transistor having a nitrogen incorporated epitaxially grown gate dielectric and method of making same 

6,274,433

Methods and arrangements for forming a floating gate in non-volatile memory semiconductor devices 

6,274,420

Sti (shallow trench isolation) structures for minimizing leakage current through drain and source silicides 

6,274,419

Trench isolation of field effect transistors 

6,274,415

Self-aligned Vt implant 

6,274,396

Method of manufacturing calibration wafers for determining in-line defect scan tool sensitivity 

6,274,289

Chemical resist thickness reduction process 

6,273,961

Method for cleaning semiconductor processing equipment by reducing particles 

6,273,409

Locking screw mechanism that requires minimized loosening force 

6,272,393

Efficient tool utilization using previous scan data 

6,272,392

Methodology for extracting effective lens aberrations using a neural network 

6,272,169

Software based modems that interact with the computing enviroment 

6,272,046

Individual source line to decrease column leakage 

6,272,043

Apparatus and method of direct current sensing from source side in a virtual ground array 

6,271,602

Method for reducing the susceptibility to chemical-mechanical polishing damage of an alignment mark formed in a semiconductor substrate 

6,271,591

Copper-aluminum metallization 

6,271,563

MOS transistor with high-K spacer designed for ultra-large-scale integration 

6,271,154

Methods for treating a deep-UV resist mask prior to gate formation etch to improve gate profile 

6,271,151

Method and apparatus for controlling the thickness of a gate oxide in a semiconductor manufacturing process 

6,271,132

Self-aligned source and drain extensions fabricated in a damascene contact and gate process 

6,271,122

Method of compensating for material loss in a metal silicone layer in contacts of integrated circuit devices 

6,271,120

Method of enhanced silicide layer for advanced metal diffusion barrier layer application 

6,271,114

System for adjusting the size of conductive lines based upon the contact size 

6,271,112

Interlayer between titanium nitride and high density plasma oxide 

6,271,095

Locally confined deep pocket process for ULSI mosfets 

6,271,087

Method for forming self-aligned contacts and local interconnects using self-aligned local interconnects 

6,270,929

Damascene T-gate using a relacs flow 

6,270,635

Consistent plating system for electroplating 

6,270,580

Modified material deposition sequence for reduced detect densities in semiconductor manufacturing 

6,270,579

Nozzle arm movement for resist development 

6,269,459

Error reporting mechanism for an AGP chipset driver using a registry 

6,269,454

Maintaining object information concurrent with data optimization for debugging 

6,269,436

Superscalar microprocessor configured to predict return addresses from a return stack storage