HyperTransport Consortium Leader Brings Clarity to Interconnect Technology Landscape
Posted By Van Smith
Date: August 8, 2001
HyperTransport's consortium leader framed the current interconnect landscape, showing that not only does HyperTransport enjoy nearly a three year head start, but that the technology is complimentary to Intel's proposed Arapahoe.
As Arapahoe is being hammered out to be handed over to the PCI-SIG for formalization, HyperTransport belongs to the HyperTransport Consortium and not AMD. The leader of the HyperTransport Consortium, Gabriele Sartori, spoke with Van's Hardware Journal and brought clarity to the current interconnect confusion.
Today Versus Tomorrow
The comparisons being made in the media and apparently by Intel between Arapahoe and HyperTransport is a contrast of future versus current technology. While Intel points to per-pin bandwidth of 2.5 Gb/s versus HyperTransport's current 1.6Gb/s, the first implementations of Arapahoe are not expected until 2003, while HyperTransport is here today. The HyperTransport Consortium, which includes Sun, Apple, Transmeta, AMD and many others, already has working HyperTransport technology boasting 3.2 Gb/s and foresees higher and higher through put rates.
Intel's claim of Arapahoe scaling to 10 Gb/s per pin will be for implementation far into the future since current costs for deploying such technology would be wildly prohibitive.
When the market sees the first Arapahoe based systems in 2003, the aggregate bandwidth is likely to be only about 1 GB/s. Assuming 2.5Gb/s pin pair with four pairs of wires, this comes out to around 10 Gb/s, but because of Arapahoe's overhead, actual throughput will be reduced to about 1GB/s. In contrast, currently HyperTranport supports aggregate bandwidths up to 16 GB/s, enough to support 16 Arapahoe interfaces.
And multiple Arapahoe interfaces are necessary because the technology does not support HyperTransport's "Tunneling" mechanism. This means that for each device interface implemented with Arapahoe, a unique Arapahoe controlled must be used. To achieve a system like current PCI slots, each slot would demand a separate Arapahoe controller, driving up costs and South Bridge pin counts.
Although 16 wire versions Arapaho delivering 4GB/s of payload (taking into consideration the technology's clock recovering mechanism) can be developed, this would lead to a huge physical interface.
Instead of positioning HyperTransport as a successor technology to PCI, the HyperTransport Consortium foresees the technology as leveraging current and future bus technologies such as DDR PCI-X which can deliver form 2 or 4 GB/s depending on the implementation, and now Arapahoe.
Utilizing its superior latency characteristics and cheaper implementation costs, HyperTransport makes much more sense as a pervasive chip-to-chip interconnect, while leveraging Arapahoe in the future for a point-to-point expansion card standard.
Unlike Arapahoe, using its "Tunneling" mechanism, HyperTransport can support multiple buses simultaneously while not driving up South Bridge pin counts.
HyperTransport also enjoys lower implementation costs for 4-bit wide interfaces and up thanks to having a clock every eight bits, while Arapahoe has an embedded clock for each bit.
From a performance perspective Sartori made the analogy that HT is a T1 and Arapahoe is DSL. Some predicted DSL would undermine T1 lines, but that has not happened due to the particular advantages of T1.
If looking for a better comparison with HyperTransport, Rapid I/O is foreseen as HT's real competitor. However, since Rapid I/O was designed to ignore some PC compatibility issues, it will likely only see widespread deployment in the embedded space.
Sartori is expecting HyperTransport to host dual channel PCI implementation supporting fully concurrent data streams to arrive no later than AMD's Hammer platform next year, although he hinted that there might be a similar product for another platform before then.
Market penetration for HyperTransport will be significant since HT will be on any platform that carries AMD. Sartori also suggested that a major chipset player will soon announce a HyperTransport enabled Intel platform as well.
Finally, by joining the HT Consortium, the technology will be royalty free forever. In contrast, Arapahoe may carry royalties because it is based on technology that potentially may demand royalty payments in the future.