Future Processing Techniques

By Nils Dahl

Date: April 30, 2002

This is fairly high tech stuff that is based on really old concepts of distributing parts of a system's workload onto specialized silicon.  http://zdnet.com.com/2100-1103-892836.html

This article about IBM's new Power 5 processor illustrates forward looking concepts that will help IBM increase its server market. The Power 5 will contain optimized logic that handles the conversion of TCP/IP packets back into blocks of data - see the Fast Path section of the article near the end of the page.

Why bother mentioning this? Well, AMD's Hammer systems of processing nodes, linked via Hypertransport interfaces, could do such things right now, given Hypertransport chips that funnel data from a specialized processor (or a general purpose processor that is running a very simple block of code) to another general purpose processor linked via Hypertransport. This idea is just like having mpeg encoder/decoder chips in subsystems that work with general purpose processors - or using modems that contain highly specialized processing nodes to do computation intensive but simple jobs far more efficiently than a general purpose processor can. Ooops, monster sentences again.

In simpler terms, innovative uses of Hypertransport to link general purpose and special purpose processing nodes could produce much faster, lower cost functionality that would compete with IBM's more elegant 'one chip' solutions will, albeit at slower rates. While everyone is still looking at processor speeds and performance, the real secret to AMD's success will be use of Hypertransport to distribute processing workload over multiple specialized nodes - perhaps with a 'single smp system' working in the classic manner at one end of the data flow path. Of course design costs can be kept lower by using general purpose Hammer nodes that are dedicated to simple processing chores.

Consider another classic example of this - SCSI. The intelligent controller does most of the work of locating, reading, and holding data in buffers while the main system resumes other tasks. In the world of OpenGL video cards, where the intelligent video system does all the specialized drawing and coloring work. Postscript subsystems in laser printers, where the risc-based system converts postscript language into bit-mapped images all by itself, are another good example.

IBM is simply extending these ideas to another field - the very burdensome conversion of data into TCP/IP packets or the reverse. In my opinion, innovative uses of Hammer and Hypertransport could easily duplicate such approaches and provide enormous performance increases quite easily.

Intel, of course, is still stuck with the notion of the central processing node doing everything - and getting upgraded regularly to handle more complex workloads.



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