Hammer Analysis
By Nils Dahl
Date: October 17, 2001
I just reviewed the 45 page Hammer processor pdf file that got released late Monday. I am halfway between a nasty giggle and a full out roar of hilarity.
Ah, there will be lots of people doing lots of very fine reviews of the new Hammer architecture. I mean - an 8-way system that can take 64 DDR SDRAM DIMMS (8 modules per node) is very close to a ...
Well, let me spell it out. The real key to Hammer is three HyperTransport interfaces, one being a dedicated interface to fast I/O. There is one for I/O and two more for communication between processors. Yeah, super-high speed parallel links between processors.
This is much closer to a very fancy minicomputer than to the good old Xeon with its backside cache. This is a basic scheme for a small supercomputer that can handle certain special types of work very nicely.
Er, breaking encryption for example. Maybe sharing loads dynamically for rapid generation of 3D objects and scenes - a field that once was the province of high end manufacturing firms that wanted a 3D cad animation of complex assemblies in action but now is widely used in movies and other neat stuff.
Think of it as an Inmos Transputer on steroids. With AMD's new Hammer scheme, one processor can be handling the retrieval of data from hard drives and then pass this directly on to another processor that is generating web pages or doing movie effects processing - and that data goes from the second processor directly to your average, everyday 8X AGP card. Or you can get fancier with your choice of 4 or 8 way systems.
Are there any equivalents that work already? Well, Hammer can be used somewhat like a small Beowulf cluster but with much faster links between working nodes. Or, from another viewpoint, Hammer can be easily used to provide a classic "back end database system" plus "web site generating front end system" all on one motherboard and with super-fast direct data feeds from the back end to the front end.
Yes, as I kinda expected, Hammer leaves out the nVidia graphics subsystem and puts in its place that second HyperTransport interface and, of course, the processor itself. No more slow wire trace connection between processor and Northbridge.
Gee, those 64-bit wide HyperTransport paths between processors look neat.
This Hammer design quite obviously was derived from some far more sophisticated concepts than are currently in use by Intel for its own kinda cheesy smp control system, a scheme that is mostly software driven.
But my expertise does not extend to the architecture of today's minicomputers. I would imagine that IBM's S/390 processor array uses similar interconnect techniques - although far more advanced. And I just don't have the power entry for a 390 mainframe.
Now we are faced with a major challenge. Linux and Windows XP just are not sophisticated enough to take on the Hammer design - even though most of the code will run on a Hammer processor. The key to Hammer is new compilers that produce code structures more suited to Hammer's strong points. There definitely are going to be some challenges to face and deal with.
One key challenge is the mostly traditional approach to system designs, where a server farm has bays of back end database servers feeding page components to bays of front end html servers. Hammer drastically changes that way of configuring hardware AND separating the various software functionalities into separate worlds.
Hammer might be in the same class as a custom Sun 8 way server or it might be somewhat superior in certain types of work. If there is a "big iron" performance area where Hammer is weaker, it will be in floating point speed.
In summary, I will opine that Hammer will easily replace Intel's best technologies in all the markets that Intel currently is trying to enter. This, of course, is the Sledgehammer system that will begin arriving late in 2002.
Just what the Clawhammer will consist of remains to be seen. Clawhammer is likely to be a single/dual processor system that requires a separate 8X AGP card (or slower) and represents a step up from the low end market. Low end means what we now are seeing as AMD's new fast Athlon XP and nForce package.
And a market prediction. Next year's low cost mass market designs will be Athlon XP/nForce [ed: Thoroughbred/Barton Athlons with similarly evolved nForce chipsets] combinations - and they will sell in the price range that current Duron systems do now. I base this projection on the economies of mass production that come with very high volumes of high yield designs as the designs mature.
And now to read a new book. Oh, I will put on my Cheshire Cat smile -- that famous smile that lingered long after the cat itself had vanished.
A new day has begun.
nils dahl
just a smiling old man
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