Revisit: Sartori Talks HyperTransport, Arapahoe
Posted By Van Smith
Date: August 11, 2001
HyperTransport's consortium leader framed the current interconnect landscape, showing that not only does HyperTransport enjoy nearly a three year head start, but that the technology is complimentary to Intel's proposed Arapahoe.
As Arapahoe is being hammered out to be handed over to the PCI-SIG for formalization, HyperTransport technology exists today and is a pivotal technology in products like NVIDIA's nForce. HyperTransport is commonly attributed to AMD, but the technology now belongs to the HyperTransport Consortium. The leader of this organization, Gabriele Sartori, spoke with Van's Hardware Journal and brought clarity to the current interconnect confusion.
Today Versus Tomorrow
The comparisons being made in the media and apparently by Intel between Arapahoe and HyperTransport is a contrast of future versus current technology. While Intel points to per-pin bandwidth of 2.5 Gb/s (Gb/s = 1 billion bits per second) versus HyperTransport's current 1.6 Gb/s, the first implementations of Arapahoe are not expected until 2003, while HyperTransport is here today. The HyperTransport Consortium, which includes Sun, Apple, Transmeta, Cisco, NVIDIA, AMD and many others, already has working HyperTransport technology boasting 3.2 Gb/s and foresees higher and higher throughput rates.
Intel's claim of Arapahoe scaling to 10 Gb/s per pin will be for implementations far into the future since current costs for deploying such technology would be wildly prohibitive. Additionally, there are no technical barriers preventing the evolving HyperTransport specification from also reaching this level of per-pin bandwidth.
When the market sees the first Arapahoe based systems in 2003, the aggregate bandwidth is likely to be only about 1 GB/s (GB/s = 8 Gb/s = 1 billion bytes per second = 8 billion bits per second). Assuming 2.5 Gb/s pin pair with four pairs of wires, this comes out to 10 Gb/s, but because of Arapahoe's overhead, actual throughput will be reduced to about 1GB/s. In contrast, HyperTranport currently supports aggregate bandwidths up to 16 GB/s (32 bit bus width x 2 @ 2 GHz link speed), which is enough to support up to 15 or 16 Arapahoe interfaces.
Tunnel Devices reduce South Bridge pin counts
And multiple Arapahoe interfaces are necessary because the technology does not support HyperTransport's "Tunneling" mechanism. Device interfaces can be "daisy chained" on a HT bus, but for each device interface implemented with Arapahoe, a unique Arapahoe controller must be used. To achieve an expansion system similar to current PCI slots, each Arapahoe "slot" would demand a separate Arapahoe controller, driving up costs and South Bridge pin counts.
So unlike Arapahoe, HyperTransport can use "Tunnel Devices" to support multiple busses simultaneously while keeping South Bridge pin counts static.
Although 16 wire versions of Arapahoe delivering 4 GB/s of payload (taking into consideration the technology's clock recovering mechanism) can be developed, such versions would lead to a huge physical interface especially when considering the possibility that multiple interfaces might be necessary.
HyperTransport is for chip-to-chip interconnects; Arapahoe is the new PCI
Instead of positioning HyperTransport as a successor to PCI, the HyperTransport Consortium foresees HT as leveraging current and future bus technologies such as DDR PCI-X (which can deliver either 2 or 4 GB/s depending on the implementation), and, when it becomes available in 2003, Arapahoe (tentatively called PCI 3.0).
A successful chip-to-chip link must be economical to incorporate. Arapahoe has an embedded clock for each bit. Thanks in part to having a clock only every eight bits, HyperTransport enjoys lower implementation costs for 4-bit wide interfaces and up.
Utilizing its superior latency characteristics and cheaper implementation costs, HyperTransport makes much more sense as a pervasive chip-to-chip interconnect, where it can exploit Arapahoe in the future for a point-to-point expansion device interface standard.
From a performance perspective Sartori made the analogy that HT is like a T1 Internet pipe and Arapahoe is like DSL. Since both technologies brought similar bandwidth claims, some predicted DSL would undermine the use of T1 lines. But that has not happened due to the particular advantages of T1, such as commanding absolutely unshared, dedicated bandwidth. Where HT differs from T1, however, is that HyperTransport should be more inexpensive than its rivals while T1 remains expensive.
If looking for a better comparison with HyperTransport, Rapid I/O is foreseen as HT's real competitor. However, since Rapid I/O was designed to ignore certain PC compatibility issues, this technology (which is also more expensive than HT) will likely only see widespread deployment in the certain corners of the embedded space or in asymmetric multiprocessing applications.
HyperTransport enabled Intel processor based chipset near
Sartori anticipates that a HyperTransport implementation hosting two PCI channels and supporting fully concurrent data streams to arrive no later than AMD's Hammer platform next year. Sartori also hinted that there might be a similar product for another platform before that time.
HyperTransport market penetration will be significant since HT will be on any platform that carries AMD. Sartori suggested that with AMD anticipating a 30% market share of PC processors by the end of this year, this could mean as many as 50 million HyperTranport enabled AMD systems alone could be shipping per year in the near future.
Sartori also suggested that a major chipset player will soon announce a HyperTransport enabled Intel platform to bring HT even greater market share.
HyperTransport is royalty free while Arapahoe may not be
A final consideration are royalty payments. When a company joins the HyperTransport Consortium, the HT technology will be royalty free to that company forever. In contrast, Arapahoe may carry royalties because it is based on technology that potentially may demand royalty payments in the future.